ITS Upgrade Project: Designing the Technology (Working Group 3)
The 3rd working Group (WG3) is responsible for studying and developing new detector technologies, designing and evaluating architectures and layout concepts for the upgrade of the ALICE ITS. WG3 translates the requirements defined by the first two working groups (WG1 and WG2) into technical specifications and tests which detector technology can be applied and will meet the performance requirements. The technical choices must also comply with the mechanical and cooling constraints discussed in WG4. The new ITS will be arranged in 7 barrel layers around the interaction point using silicon detectors. Two layouts are being discussed: an all pixel solution using monolithic silicon pixel detectors and a mixed layout with three pixel layers and four silicon strip layers. In total the new ITS will cover a total area of about 10 m2.
For the innermost layers hit densities of up to 150 hits per cm2 are expected in heavy ion collisions. Thus the use of a highly segmented tracking detector is mandatory to unambiguously distinguish the individual tracks. As a consequence for the innermost three layers silicon pixel detectors will be employed. Typical pixel sizes under study are in the order of 20 µm x 20 µm. As we move to larger radii the hit density quickly decreases to about 1 hit per cm2 in the outermost layers, therefore allowing the use of silicon strip detectors, which are still highly segmented in r-φ direction (~ 80 µm pitch), but have strip lengths of about 2 cm in z-direction. The layout options considered for the strip layers follow closely the present strip layers installed in ALICE.
Two basic concepts of pixel detectors are being studied for the ALICE ITS upgrade: hybrid silicon pixel detectors and monolithic silicon pixel detectors. Both concepts are schematically shown in the figures below. While hybrid silicon pixel detectors present the state of the art technology used in all LHC experiments, monolithic silicon pixel detectors have made impressive progress in recent years and are for example being installed in the STAR experiment. Hybrid silicon pixel detectors consist of two silicon components (ASIC and Sensor), which are connected using flip-chip bonding. Each pixel cell on the sensor is directly connected to the corresponding cell in the ASIC using a solder ball of typical diameter of 20-30 µm as is shown in the scheme in Figure 1. This interconnection technology has been well established and is employed in present pixel systems. However, it presents an additional level of complexity and is due to its cost a limiting factor for large area systems.
Figure 1: Hybrid silicon pixel detector (see Rossi,L. Fischer, P., Rohe, T. & Wemesm N. (2006). Berlin: Springer
Monolithic silicon pixel detector (see Stanitzki, M.(2010). Nucl.Instr. and Meth.A doi: 10.1016/n.jima.2010.11.166
Within the WG3 prototypes for both pixel technologies have been realized in the course of the past year. One of the main challenges is clearly the limitation in allowed material budget. This is necessary in order to improve the impact parameter resolution at low pT by about a factor of 3. A total of 0.3% X0 per layer is about a factor 3 less than used in the present ALICE silicon pixel detector, which is already the pixel detector with the lowest material budget of all LHC detectors. The thickness requirements for each component are therefore stringent. Silicon thicknesses of 50 µm in case of monolithic detectors or 100+50 µm in case of hybrid pixel detectors require special developments, which have been pursued within the WG3 community.
Figures 3 and 4 show two examples of prototype developments carried out on monolithic and hybrid pixel detectors. Figure 3 shows the MIMOSA32 prototype chip, one of several monolithic prototype pixel chips that have been designed and produced in a 0.18 µm CMOS process . This smaller feature size process enhances the radiation resistance compared to the previous generation of monolithic pixel detectors and provides the possibility to use a high resistive epitaxial layer inside the chip for particle detection.
Extensive radiation tests have been carried out and are being continued on different prototypes produced in this process to ensure the full compatibility with the operation in the ALICE environment. Figure 4 shows a side view taken with a Scanning Electron Microscope (SEM) of a hybrid pixel assembly which has successfully been produced using a 50 µm thick chip connected to a 100-µm thick sensor. Both parts are connected using micro bump bonds of about 25µm diameter.
Figure 3 :MIMOSA32 monolithic prototype chip (top) and measured S/N ratio of irradiated and non-irradiated MIMOSA32 chips in a testbeam at the CERN SPS (bottom) (also see TowerJazz). The lower figure shows S/N measurments taken at two different operating temperatures (15 °C and 30°C ) for a non-irradiated chip (yellow and green curve) and a chip that has been irradiated with X-rays and neutrons to the radiation levels expected for the innermost layer of the new ITS. (Conceptual Design Report of the ALICE ITS Upgrade, CERN-LHCC-2012-013
The constraints in material budget not only require the use of thin silicon detector elements and specially adapted mechanics and cooling, but also the development of a low mass interconnection system to provide power and signal connections. Low-mass bus cables made of aluminium and polyimide are being developed and studied using measurements and simulation of the electrical characteristics. The working group also embarked in the study of alternative connection techniques compared to aluminium wedge wire bonding for the connection between the chips and the bus cable. Prototypes have been developed using several different techniques such as laser soldering or gold-stud bonding.
Figure 4: Scanning Electron Microscope (SEM) image (side view) of a hybrid silicon pixel assembly (100 µm sensor and 50 µm chip). The bump bonds have a diameter of about 25 µm and connect each pixel cell in the sensor with the corresponding cell in the pixel chip. The assembly work was done by IZM (Fraunhofer-Institute for Reliability and Microintegration (IZM), D-13355 Berlin, Germany).
In the case of an all pixel solution for the upgrade of the ALICE ITS, the design of the outermost layer requires specific attention in terms of power dissipation and module layout. The outermost layer will stretch over almost 150 cm, with the constraint that at least the signal connections will only be possible from one side. A design with a low power consumption is mandatory, simply due to the fact of the large surface.
Working group 3 is a group of physicists, engineers and technicians, enthusiastically embarking in the adventure of finding an innovative and reliable technical solution for the upgrade of the ALICE ITS. In this endeavour several boundaries have to be overcome. Clearly the limited available material budget is one of it. A low power dissipation teamed up with a very high granularity and pixel sizes of the order of 20 µm is certainly another one. In addition we explore new technological options such as the 0.18 µm CMOS process and new techniques for interconnections.
I would like to thank all the members in the teams that participate in the WG3 activities and which are based in many institutes around the world. Many of these have already worked on the construction of the present ITS, others including leading institutes in the development of monolithic pixel detectors have newly joined the project.